MIN PULSE WIDTH TIMING CHECK The Silent Timing Trap Lurking In Every Sub-5nm Design
semiwiki.com·10h
📏Linear Scanning
smartgo: I wish for a Go-like language with Rust-like pointers
iio.ie·43m
🔒Rust Borrowing
The Role of AI in Next-Gen Chip Design
dev.to·3h·
Discuss: DEV
🔌Microcontrollers
Cuckoo hashing improves SIMD hash tables
reiner.org·1d·
Discuss: Lobsters, Hacker News, r/rust
🏗️Hash Tables
Property-based testing of batch-invariant operations
mmaaz.ca·4h·
Discuss: Hacker News
🎲Property Testing
Highly concurrent in-memory counter in GoLang
engineering.grab.com·3h
🧠Memory Models
Opti's Claude 4.5 Sonnet "vibe coding" report
stacker.news·15h
🔬Nanopasses
A Primer on Memory Consistency and Cache Coherence, Second Edition
link.springer.com·9h·
Discuss: r/programming
🧠Memory Models
XiangShan Vector Floating-Point Unit Design
docs.xiangshan.cc·1d·
Discuss: Hacker News
🎯Bit Vectors
Adding Stride Scheduling to Xv6
nickchandler.dev·18h·
Discuss: Lobsters, Hacker News
🔄Go Scheduler
A gentle introduction to GEMM using MMA tensor cores
am17an.bearblog.dev·3d·
Discuss: Hacker News
📏Linear Memory
Measuring Reorder Buffer Capacity
blog.stuffedcow.net·3d·
Discuss: Lobsters, Hacker News
📝Register Allocation
std::ranges may not deliver the performance that you expect
lemire.me·6h·
Discuss: Hacker News
🏃Escape Analysis
Homerow Mods at 100+ WPM
reddit.com·6h·
Discuss: r/ErgoMechKeyboards
💻Terminal Emulators
🔍 Understanding Global Object Search Order in Uniface 10.4
dev.to·20h·
Discuss: DEV
🌉Language Bindings
Fun with HyperLogLog and SIMD
vaktibabat.github.io·1d·
Discuss: Hacker News, r/rust
🔢Bit Manipulation
Why We Need SIMD
parallelprogrammer.substack.com·26m·
Discuss: Substack
🔀SIMD Programming
LLMs are badly misaligned
lesswrong.com·13h
✅Type Checking
Huawei's new open source technique shrinks LLMs to make them run on less powerful, less expensive hardware
venturebeat.com·2d
🔄Binary Translation
How Much Should You Tell Your AI Agent?
raymondyxu.com·9h·
Discuss: Hacker News
💬Interactive REPLs